Technical Field
The present disclosure relates to split-gate memory cells each comprising a selection transistor section and a floating-gate transistor section. The selection transistor section comprises a selection gate and the floating-gate transistor section comprises a floating gate and a control gate.
Description of the Related Art
So-called “split-gate” memory cells are conventionally programmed by hot-electron injection (or “hot-carrier injection”). Compared to tunnel-effect programming, programming by hot electrons has the advantage of being short, generally 100 times shorter than tunnel-effect programming. The programming time of a memory cell by hot-electron injection is typically of the order of a few microseconds compared to a few milliseconds for tunnel-effect programming.
During hot-electron programming, the two transistor sections of the memory cell cooperate in order to inject electric charges into the floating gate. The selection transistor section has a conductive channel in which a current appears which comprises high kinetic energy electrons, referred to as “hot electrons”. When this current reaches the conductive channel of the floating-gate transistor section, an injection zone appears where the high energy electrons are injected into the floating gate under the effect of a transverse electric field created by the voltage applied to the control gate.
FIG. 1 shows the arrangement of a conventional split-gate memory cell C1i,j in a word line WLi of a memory array. The selection gate SG of the selection transistor ST section of the memory cell is connected to a selection line SLi and the control gate CG of the floating-gate transistor FGT section is connected to a control gate line CGLi. The drain D of the selection transistor section is connected to a bit line BLj and the source S of the floating-gate transistor FGT section is connected to a source line SCLi. The selection SLi, control gate CGLi and source SCLi lines are parallel and linked to all the memory cells of the word line. The bit line BLj is transverse to the lines SLi, CGLi, SCLi and is also connected to memory cells belonging to other word lines (not represented).
The selection line SLi receives a selection voltage VSi, the control gate line CGLi receives a gate voltage VGi and the source line SCLi receives a source voltage VSC. Voltage VG is generally high, for example 10V, to generate in the channel of the floating-gate transistor FGT section a transverse electric field favoring the injection of electrons into the floating gate. Voltage VSC is sufficiently high, for example 4V, to ensure the conduction of the memory cell. Voltage VS is generally set at a value greater than the threshold voltage of the selection transistor section, for example between 1V and 3V. A programming current passes through the memory cell and the bit line BLj. A flow of electrons circulating in the opposite direction to the current passes through the channel of the selection transistor section until it reaches the injection point into the channel of the floating-gate transistor section.
Offsetting their good injection performance, split-gate memory cells have the disadvantage of occupying more semiconductor surface than conventional flash memory cells, also programmed by hot-electron injection but comprising only one control gate.
U.S. Pat. No. 5,495,441 discloses a so-called “split-gate” memory cell the selection transistor section of which is arranged vertically to reduce the footprint of the memory cell. FIG. 2 corresponds to FIG. 7 of that document and shows a cross-section of the structure of such a memory cell. The numerical references in FIG. 2 are those of the original FIG. 7 of the aforementioned document. The memory cell C2 shown in FIG. 2 comprises a trench etched in a substrate (27) after forming a floating gate FG (28) made of polysilicon (polycrystalline silicon) above the substrate. The trench has then been covered with an oxide layer (200a, 200b). A conductive layer made of polysilicon (26) has then been deposited on the entire memory cell. The conductive layer (26) has a portion extending in the trench and forming a vertical selection gate SG, a portion extending above the floating gate FG (28) forming a horizontal control gate CG, the rest of the conductive layer forming a selection line SL of the memory cell. A doped region (21) implanted in the substrate forms a bit line BL and doped regions (20) implanted at the bottom of the trench form “source bit lines” SBL that are parallel to the bit line BL (21). The memory cell C2 thus comprises a selection transistor ST section having a vertical channel of length L1, and a floating-gate transistor FGT section having a horizontal channel of length L2, which cooperate to form a transistor having a channel of length L1+L2. The control CG and selection SG gates of the two transistor FGT, ST sections are formed by the same conductive layer (26) and therefore form a single component. The memory cell C2 is formed together with a memory cell C2′ linked to the same selection line SL (26) and to the same bit line BL (21), but to a different “source bit line” SBL′ (20).
As shown in FIG. 3, this structure of memory cell C2, C2′ uses a memory array architecture that differs greatly from the conventional architecture shown in FIG. 1. The sources S of the selection transistor ST sections of the two twin memory cells are connected to the “source bit lines” SBL (20), SBL′ (20) that are parallel to the bit line BL (21). The selection line SL (26), and the gates SG (26) and CG (26) of the memory cells are at the same electric potential, the gates SG and CG thus forming a single selection/control gate.
This memory cell structure offers a low footprint thanks to the vertical arrangement of the selection transistor section. On the other hand, it involves a multiplication of the number of source lines, in the form of “source bit lines” SBL, thus entailing a multiplication of the means for switching voltages in the memory array. For example, a word line comprising 1,024 memory cells will have 512 bit lines and 1,024 “source bit lines” parallel to the bit lines, compared to 1,024 bit lines and a single source line in a conventional architecture of the type shown in FIG. 1.
Furthermore, as the control CG and selection SG gates have the same electric potential as they are formed by the same polysilicon layer (26), it is not possible to apply different voltages to them to optimize the injection performance with the efficiency offered by a conventional split-gate memory cell of the type represented in FIG. 1.
Finally, the gate oxide 200a that covers the trench is formed at the same time as a lateral oxide 200b that isolates the selection gate SG from the floating gate FG. It is not therefore possible to separately control the thickness of the gate oxide 200a and that of the lateral oxide 200b. This manufacturing method thus offers little flexibility for the control of the electrical characteristics of the memory cell, in particular its injection performance, its threshold voltage in the vertical channel region L1, and its breakdown voltage.
It could thus be desirable to provide an enhanced split-gate memory cell structure, and a method of manufacturing such a memory cell.